mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 484
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mc9s12hz256v2
Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12HZ256V2.pdf
(692 pages)
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Chapter 16 Timer Module (TIM16B8CV1)
16.3.2.4
Read: Anytime
Write: Anytime
16.3.2.5
The 16-bit main timer is an up counter.
A full access for the counter register should take place in one clock cycle. A separate read/write for high
byte and low byte will give a different result than accessing them as a word.
484
OC7M[7:0]
OC7D[7:0]
Reset
Reset
Reset
Field
Field
7:0
7:0
W
W
W
R
R
R
TCNT15
OC7D7
TCNT7
Output Compare 7 Mask — Setting the OC7Mx (x ranges from 0 to 6) will set the corresponding port to be an
output port when the corresponding TIOSx (x ranges from 0 to 6) bit is set to be an output compare.
Note: A successful channel 7 output compare overrides any channel 6:0 compares. For each OC7M bit that is
Output Compare 7 Data — A channel 7 output compare can cause bits in the output compare 7 data register
to transfer to the timer port data register depending on the output compare 7 mask register.
Output Compare 7 Data Register (OC7D)
Timer Count Register (TCNT)
15
0
0
0
7
7
set, the output compare action reflects the corresponding OC7D bit.
TCNT14
OC7D6
TCNT6
14
0
0
0
6
6
Figure 16-9. Output Compare 7 Data Register (OC7D)
Figure 16-10. Timer Count Register High (TCNTH)
Figure 16-11. Timer Count Register Low (TCNTL)
Table 16-4. OC7M Field Descriptions
Table 16-5. OC7D Field Descriptions
TCNT13
OC7D5
TCNT5
MC9S12HZ256 Data Sheet, Rev. 2.05
13
0
0
0
5
5
TCNT12
OC7D4
TCNT4
12
0
0
0
4
4
Description
Description
TCNT11
OC7D3
TCNT3
11
0
0
0
3
3
TCNT10
OC7D2
TCNT2
10
0
0
0
2
2
OC7D1
TCNT9
TCNT1
Freescale Semiconductor
0
0
0
1
9
1
OC7D0
TCNT8
TCNT0
0
0
0
0
9
0
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