mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 575

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 21
Multiplexed External Bus Interface (MEBIV3)
21.1
This section describes the functionality of the multiplexed external bus interface (MEBI) sub-block of the
S12 core platform. The functionality of the module is closely coupled with the S12 CPU and the memory
map controller (MMC) sub-blocks.
Figure 21-1
pins that are accessible externally. On some chips, these may not all be bonded out.
The MEBI sub-block of the core serves to provide access and/or visibility to internal core data
manipulation operations including timing reference information at the external boundary of the core and/or
system. Depending upon the system operating mode and the state of bits within the control registers of the
MEBI, the internal 16-bit read and write data operations will be represented in 8-bit or 16-bit accesses
externally. Using control information from other blocks within the system, the MEBI will determine the
appropriate type of data access to be generated.
21.1.1
The block name includes these distinctive features:
Freescale Semiconductor
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External bus controller with four 8-bit ports A,B, E, and K
Data and data direction registers for ports A, B, E, and K when used as general-purpose I/O
Control register to enable/disable alternate functions on ports E and K
Mode control register
Control register to enable/disable pull resistors on ports A, B, E, and K
Control register to enable/disable reduced output drive on ports A, B, E, and K
Control register to configure external clock behavior
Control register to configure IRQ pin operation
Logic to capture and synchronize external interrupt pin inputs
Introduction
Features
is a block diagram of the MEBI. In
MC9S12HZ256 Data Sheet, Rev. 2.05
Figure
21-1, the signals on the right hand side represent
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