mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 451
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mc9s12hz256v2
Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12HZ256V2.pdf
(692 pages)
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15.3.2.5
The PWMCAE register contains six control bits for the selection of center aligned outputs or left aligned
outputs for each PWM channel. If the CAEx bit is set to a 1, the corresponding PWM output will be center
aligned. If the CAEx bit is cleared, the corresponding PWM output will be left aligned. Reference
Section 15.4.2.5, “Left Aligned Outputs,”
detailed description of the PWM output modes.
Read: anytime
Write: anytime
Freescale Semiconductor
Reset
W
R
PWM Center Align Enable Register (PWMCAE)
0
0
7
Write these bits only when the corresponding channel is disabled.
= Unimplemented or Reserved
PCKB2
PCKA2
Figure 15-7. PWM Center Align Enable Register (PWMCAE)
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
6
Table 15-6. Clock B Prescaler Selects
Table 15-7. Clock A Prescaler Selects
CAE5
PCKB1
MC9S12HZ256 Data Sheet, Rev. 2.05
PCKA1
0
5
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
and
Section 15.4.2.6, “Center Aligned Outputs,”
CAE4
NOTE
PCKB0
0
4
PCKA0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
CAE3
0
3
Value of Clock B
Chapter 15 Pulse-Width Modulator (PWM8B6CV1)
Value of Clock A
Bus Clock / 128
Bus Clock / 128
Bus Clock / 16
Bus Clock / 32
Bus Clock / 16
Bus Clock / 32
Bus Clock / 64
Bus Clock / 64
Bus Clock / 2
Bus Clock / 4
Bus Clock / 8
Bus Clock / 2
Bus Clock / 4
Bus Clock / 8
Bus Clock
Bus Clock
CAE2
0
2
CAE1
0
1
for a more
CAE0
0
0
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