mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 164

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 4 Port Integration Module (PIM9HZ256V2)
4.6
4.6.1
Port AD generates an edge sensitive interrupt if enabled. It offers eight I/O pins with edge triggered
interrupt capability in wired-or fashion. The interrupt enable as well as the sensitivity to rising or falling
edges can be individually configured on per pin basis. All eight bits/pins share the same interrupt vector.
Interrupts can be used with the pins configured as inputs (with the corresponding ATDDIEN1 bit set to 1)
or outputs.
An interrupt is generated when a bit in the port interrupt flag register and its corresponding port interrupt
enable bit are both set. This external interrupt feature is capable to wake up the CPU when it is in stop or
wait mode.
A digital filter on each pin prevents pulses
interrupt. The minimum time varies over process conditions, temperature and voltage
Table
164
4-42).
Interrupts
General
Glitch, filtered out, no interrupt flag set
Valid pulse, interrupt flag set
1
These values include the spread of the oscillator frequency over temperature,
voltage and process.
Uncertain
Ignored
Pulse
Valid
Figure 4-57. Interrupt Glitch Filter on Port AD (PPS = 0)
t
Table 4-42. Pulse Detection Criteria
ifmin
3 < t
MC9S12HZ256 Data Sheet, Rev. 2.05
t
t
pulse
pulse
pulse
t
ifmax
<= 3
>= 4
(Figure
< 4
STOP
4-58) shorter than a specified time from generating an
Bus Clock
Bus Clock
Bus Clock
Unit
Mode
3.2 < t
t
pulse
t
pulse
pulse
<= 3.2
>= 10
STOP
< 10
1
Unit
Freescale Semiconductor
s
s
s
(Figure 4-57
and