mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 403

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mc9s12hz256v2

Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
13.4.3
A 13-bit modulus counter in the baud rate generator derives the baud rate for both the receiver and the
transmitter. The value from 0 to 8191 written to the SBR[12:0] bits determines the module clock divisor.
The SBR bits are in the SCI baud rate registers (SCIBDH and SCIBDL). The baud rate clock is
synchronized with the bus clock and drives the receiver. The baud rate clock divided by 16 drives the
transmitter. The receiver has an acquisition rate of 16 samples per bit time.
Baud rate generation is subject to one source of error:
Table 13-13
MHz.
When IREN = 0 then,
Freescale Semiconductor
Integer division of the module clock may not give the exact target frequency.
SCI baud rate = SCI module clock / (16 * SCIBR[12:0])
Baud Rate Generation
lists some examples of achieving target baud rates with a module clock frequency of 10.2
SBR[12–0]
Table 13-13. Baud Rates (Example: Module Clock = 10.2 MHz)
1062
2125
4250
5795
Bits
133
266
531
17
33
66
Clock (Hz)
600,000.0
309,090.9
154,545.5
Receiver
76,691.7
38,345.9
19,209.0
9604.5
4800.0
2400.0
1760.1
MC9S12HZ256 Data Sheet, Rev. 2.05
Transmitter
Clock (Hz)
37,500.0
19,318.2
9659.1
4793.2
2396.6
1200.6
600.3
300.0
150.0
110.0
Chapter 13 Serial Communication Interface (SCIV4)
Target Baud
38,400
19,200
Rate
9600
4800
2400
1200
600
300
150
110
Error
(%)
2.3
.62
.62
.14
.14
.11
.05
.00
.00
.00
403

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