mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 228
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mc9s12hz256v2
Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12HZ256V2.pdf
(692 pages)
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Chapter 7 Analog-to-Digital Converter (ATD10B16CV4)
7.3.2.10
This read-only register contains the Conversion Complete Flags CCF15 to CCF8.
Read: Anytime
Write: Anytime, no effect
228
CCF[15:8]
Reset
Field
7:0
W
R
SC
CCF15
1
1
1
1
1
1
ATD Status Register 2 (ATDSTAT2)
0
7
Conversion Complete Flag Bits — A conversion complete flag is set at the end of each conversion in a
conversion sequence. The flags are associated with the conversion position in a sequence (and also the result
register number). Therefore, CCF8 is set when the ninth conversion in a sequence is complete and the result
is available in result register ATDDR8; CCF9 is set when the tenth conversion in a sequence is complete and
the result is available in ATDDR9, and so forth. A flag CCFx (x = 15, 14, 13, 12, 11, 10, 9, 8) is cleared when
one of the following occurs:
In case of a concurrent set and clear on CCFx: The clearing by method A) will overwrite the set. The clearing
by methods B) or C) will be overwritten by the set.
0 Conversion number x not completed
1 Conversion number x has completed, result ready in ATDDRx
• Write to ATDCTL5 (a new conversion sequence is started)
• If AFFC = 0 and read of ATDSTAT2 followed by read of result register ATDDRx
• If AFFC = 1 and read of result register ATDDRx
= Unimplemented or Reserved
CD
CCF14
0
0
0
0
0
1
0
6
Figure 7-12. ATD Status Register 2 (ATDSTAT2)
Table 7-20. Special Channel Select Coding
Table 7-21. ATDSTAT2 Field Descriptions
CCF13
CC
MC9S12HZ256 Data Sheet, Rev. 2.05
X
0
1
1
1
1
0
5
CCF12
CB
0
4
X
X
0
0
1
1
Description
CCF11
0
3
CA
X
X
0
1
0
1
CCF10
0
2
Analog Input Channel
(V
Reserved
Reserved
Reserved
RH
Freescale Semiconductor
V
+V
V
CCF9
RH
RL
0
RL
1
) / 2
CCF8
0
0
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