mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 525

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Figure 18-9
target, there is up to a one clock-cycle delay from the host-generated falling edge on BKGD to the start of
the bit time as perceived by the target. The host initiates the bit time but the target finishes it. Because the
target wants the host to receive a logic 0, it drives the BKGD pin low for 13 target clock cycles then briefly
drives it high to speed up the rising edge. The host samples the bit level about 10 target clock cycles after
starting the bit time.
Freescale Semiconductor
TARGET SYSTEM
TARGET SYSTEM
SPEEDUP PULSE
TARGET SYS.
START OF BIT TIME
TARGET SYS.
START OF BIT TIME
BKGD PIN
DRIVE AND
BKGD PIN
SPEEDUP
DRIVE TO
BKGD PIN
DRIVE TO
BKGD PIN
CLOCK
CLOCK
PULSE
HOST
PERCEIVED
HOST
PERCEIVED
shows the host receiving a logic 0 from the target. Because the host is asynchronous to the
Figure 18-8. BDM Target-to-Host Serial Bit Timing (Logic 1)
Figure 18-9. BDM Target-to-Host Serial Bit Timing (Logic 0)
HIGH-IMPEDANCE
10 CYCLES
MC9S12HZ256 Data Sheet, Rev. 2.05
10 CYCLES
R-C RISE
10 CYCLES
10 CYCLES
HIGH-IMPEDANCE
HOST SAMPLES
HIGH-IMPEDANCE
HOST SAMPLES
BKGD PIN
BKGD PIN
Chapter 18 Background Debug Module (BDMV4)
SPEEDUP PULSE
HIGH-IMPEDANCE
EARLIEST
START OF
NEXT BIT
EARLIEST
START OF
NEXT BIT
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