mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 154
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mc9s12hz256v2
Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12HZ256V2.pdf
(692 pages)
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Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.7.4
Read: Anytime. Write: Anytime.
This register enables the slew rate control and disables the digital input buffer for port pins PU[7:0].
4.3.7.5
Read: Anytime. Write: Anytime.
This register configures whether a pull-up or a pull-down device is activated on configured input pins. If
a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
154
SRRU[7:0]
PERU[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
SRRU7
PERU7
Slew Rate Port U
0 Disables slew rate control and enables digital input buffer.
1 Enables slew rate control and disables digital input buffer.
Pull Device Enable Port U
0 Pull-up or pull-down device is disabled.
1 Pull-up or pull-down device is enabled.
Port U Slew Rate Register (SRRU)
Port U Pull Device Enable Register (PERU)
0
0
7
7
SRRU6
PERU6
Figure 4-47. Port U Pull Device Enable Register (PERU)
0
0
6
6
Figure 4-46. Port U Slew Rate Register (SRRU)
Table 4-33. SRRU Field Descriptions
Table 4-34. PERU Field Descriptions
SRRU5
PERU5
MC9S12HZ256 Data Sheet, Rev. 2.05
0
0
5
5
SRRU4
PERU4
0
0
4
4
Description
Description
SRRU3
PERU3
0
0
3
3
SRRU2
PERU2
0
0
2
2
SRRU1
PERU1
Freescale Semiconductor
0
0
1
1
SRRU0
PERU0
0
0
0
0
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