mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 143

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

4.3.5
Port S is associated with the serial peripheral interface (SPI) and serial communication interface (SCI0).
Each pin is assigned to these modules according to the following priority: SPI/SCI0 > general-purpose I/O.
When the SPI is enabled, the PS[7:4] pins become SS, SCK, MOSI, and MISO respectively. Refer to the
SPI block description chapter for information on enabling and disabling the SPI.
When the SCI0 receiver and transmitter are enabled, the PS[1:0] pins become TXD0 and RXD0
respectively. Refer to the SCI block description chapter for information on enabling and disabling the SCI
receiver and transmitter.
During reset, port S pins are configured as high-impedance inputs.
4.3.5.1
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRSx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRSx) is set to 0 (input), a read returns the value of the pin.
The SPI function takes precedence over the general-purpose I/O function if the SPI is enabled.
If enabled, the SCI0 transmitter takes precedence over the general-purpose I/O function, and the
corresponding TXD0 pin is configured as an output. If enabled, the SCI0 receiver takes precedence over
the general-purpose I/O function, and the corresponding RXD0 pin is configured as an input.
Freescale Semiconductor
SPI/SCI:
Reset
W
R
Port S
PTS7
SS
Port S I/O Register (PTS)
0
7
= Reserved or Unimplemented
PTS6
SCK
0
6
Figure 4-30. Port S I/O Register (PTS)
PTS5
MOSI
MC9S12HZ256 Data Sheet, Rev. 2.05
0
5
PTS4
MISO
0
4
0
0
3
Chapter 4 Port Integration Module (PIM9HZ256V2)
0
0
2
PTS1
TXD0
0
1
PTS0
RXD0
0
0
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