mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 407

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

13.4.5
13.4.5.1
The SCI receiver can accommodate either 8-bit or 9-bit data characters. The state of the M bit in SCI
control register 1 (SCICR1) determines the length of data characters. When receiving 9-bit data, bit R8 in
SCI data register high (SCIDRH) is the ninth bit (bit 8).
13.4.5.2
During an SCI reception, the receive shift register shifts a frame in from the RXD pin. The SCI data
register is the read-only buffer between the internal data bus and the receive shift register.
After a complete frame shifts into the receive shift register, the data portion of the frame transfers to the
SCI data register. The receive data register full flag, RDRF, in SCI status register 1 (SCISR1) becomes set,
Freescale Semiconductor
FROM TXD PIN
OR TRANSMITTER
SCRXD
LOOPS
Receiver
RSRC
RDRF/OR INTERRUPT REQUEST
Receiver Character Length
Character Reception
TDRE flag is set and immediately before writing the next byte to the SCI
data register.
If the TE bit is clear and the transmission is complete, the SCI is not the
master of the TXD pin
IDLE INTERRUPT REQUEST
RXPOL
CONTROL
LOOP
SBR12–SBR0
CLOCK
BUS
Figure 13-14. SCI Receiver Block Diagram
WAKE
DIVIDER
RAF
BAUD
ILT
RE
PE
PT
M
MC9S12HZ256 Data Sheet, Rev. 2.05
RECOVERY
DATA
CHECKING
WAKEUP
PARITY
LOGIC
INTERNAL BUS
IDLE
ILIE
RIE
Chapter 13 Serial Communication Interface (SCIV4)
H
11-BIT RECEIVE SHIFT REGISTER
8
7
SCI DATA REGISTER
RDRF
OR
6
5
R8
4
FE
NF
PE
3
2
1
0
L
RWU
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