mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 128

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mc9s12hz256v2

Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.1.6
Read: Anytime. Write: Anytime.
The Port AD Polarity Select Register serves a dual purpose by selecting the polarity of the active interrupt
edge as well as selecting a pull-up or pull-down device if enabled (PERADx = 1). The Port AD Polarity
Select Register is effective only when the corresponding Data Direction Register bit is set to 0 (input).
In pull-down mode (PPSADx = 1), a rising edge on a port AD pin sets the corresponding PIFADx bit. In
pull-up mode (PPSADx = 0), a falling edge on a port AD pin sets the corresponding PIFADx bit.
4.3.1.7
Read: Anytime. Write: Anytime.
This register disables or enables on a per pin basis the edge sensitive external interrupt associated with
port AD.
128
PPSAD[7:0]
PIEAD[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
PPSAD7
PIEAD7
Polarity Select Port AD
0 A pull-up device is connected to the associated port AD pin, and detects falling edge for interrupt generation.
1 A pull-down device is connected to the associated port AD pin, and detects rising edge for interrupt
Interrupt Enable Port AD
0 Interrupt is disabled (interrupt flag masked).
1 Interrupt is enabled.
Port AD Polarity Select Register (PPSAD)
Port AD Interrupt Enable Register (PIEAD)
0
0
7
7
generation.
PPSAD6
PIEAD6
0
0
6
6
Figure 4-8. Port AD Interrupt Enable Register (PIEAD)
Figure 4-7. Port AD Polarity Select Register (PPSAD)
Table 4-6. PPSAD Field Descriptions
PPSAD5
Table 4-7. PIEAD Field Descriptions
PIEAD5
MC9S12HZ256 Data Sheet, Rev. 2.05
0
0
5
5
PPSAD4
PIEAD4
0
0
4
4
Description
Description
PPSAD3
PIEAD3
0
0
3
3
PPSAD2
PIEAD2
0
0
2
2
PPSAD1
PIEAD1
Freescale Semiconductor
0
0
1
1
PPSAD0
PIEAD0
0
0
0
0

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