mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 342

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
12.3.2.3
The CANBTR0 register configures various CAN bus timing parameters of the MSCAN module.
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
342
SJW[1:0]
BRP[5:0]
Field
7:6
5:0
Reset:
W
R
BRP5
Synchronization Jump Width — The synchronization jump width defines the maximum number of time quanta
(Tq) clock cycles a bit can be shortened or lengthened to achieve resynchronization to data transitions on the
CAN bus (see
Baud Rate Prescaler — These bits determine the time quanta (Tq) clock which is used to build up the bit timing
(see
MSCAN Bus Timing Register 0 (CANBTR0)
0
0
0
0
1
:
SJW1
Table
0
7
SJW1
BRP4
12-7).
0
0
1
1
0
0
0
0
1
:
Table
Figure 12-4. MSCAN Bus Timing Register 0 (CANBTR0)
Table 12-6. Synchronization Jump Width
SJW0
Table 12-5. CANBTR0 Register Field Descriptions
BRP3
6
0
12-6).
0
0
0
0
1
:
Table 12-7. Baud Rate Prescaler
BRP2
MC9S12HZ256 Data Sheet, Rev. 2.05
BRP5
0
0
0
0
1
:
0
5
SJW0
BRP1
0
1
0
1
0
0
1
1
1
:
BRP4
4
0
BRP0
Description
0
1
0
1
1
:
BRP3
Synchronization Jump Width
0
3
Prescaler value (P)
2 Tq clock cycles
3 Tq clock cycles
4 Tq clock cycles
1 Tq clock cycle
BRP2
64
2
0
1
2
3
4
:
Freescale Semiconductor
BRP1
0
1
BRP0
0
0