mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 173

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mc9s12hz256v2

Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
5.3.2.2
The REFDV register provides a finer granularity for the PLL multiplier steps. The count in the reference
divider divides OSCCLK frequency by REFDV + 1.
Read: anytime
Write: anytime except when PLLSEL = 1
5.3.2.3
This register is reserved for factory testing of the CRG module and is not available in normal modes.
Read: always reads 0x0000 in normal modes
Write: unimplemented in normal modes
Freescale Semiconductor
Reset
Reset
W
W
R
R
CRG Reference Divider Register (REFDV)
Reserved Register (CTFLG)
0
0
0
0
7
7
Write to this register initializes the lock detector bit and the track detector
bit.
Writing to this register when in special mode can alter the CRG
functionality.
= Unimplemented or Reserved
= Unimplemented or Reserved
0
0
0
0
6
6
Figure 5-5. CRG Reference Divider Register (REFDV)
Figure 5-6. CRG Reserved Register (CTFLG)
MC9S12HZ256 Data Sheet, Rev. 2.05
0
0
0
0
5
5
NOTE
NOTE
0
0
0
0
4
4
REFDV3
0
0
0
3
3
Chapter 5 Clocks and Reset Generator (CRGV4)
REFDV2
0
0
0
2
2
REFDV1
0
0
0
1
1
REFDV0
0
0
0
0
0
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