mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 554
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mc9s12hz256v2
Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12HZ256V2.pdf
(692 pages)
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Chapter 19 Debug Module (DBGV1)
19.3.2.10 Debug Comparator A Register (DBGCA)
19.3.2.11 Debug Comparator B Extended Register (DBGCBX)
554
EXTCMP
PAGSEL
Reset
Reset
Reset
Field
Field
15:0
15:0
7:6
5:0
W
W
W
R
R
R
Bit 15
Bit 7
Comparator A Compare Bits — The comparator A compare bits control whether comparator A compares the
address bus bits [15:0] to a logic 1 or logic 0. See
0 Compare corresponding address bit to a logic 0
1 Compare corresponding address bit to a logic 1
Page Selector Field — If DBGEN is set in DBGC1, then PAGSEL selects the type of paging as shown in
Table
DPAGE and EPAGE are not yet implemented so the value in bit 7 will be ignored (i.e., PAGSEL values of 10 and
11 will be interpreted as values of 00 and 01, respectively.)
In BKP mode, PAGSEL has no meaning and EXTCMP[5:0] are compared to address bits [19:14] if the address
is in the FLASH/ROM memory space.
Comparator B Extended Compare Bits — The EXTCMP bits are used as comparison address bits as shown
in
15
0
0
0
7
7
Table 19-11
PAGSEL
19-11.
Figure 19-19. Debug Comparator B Extended Register (DBGCBX)
Figure 19-17. Debug Comparator A Register High (DBGCAH)
Figure 19-18. Debug Comparator A Register Low (DBGCAL)
Bit 14
Bit 6
along with the appropriate PPAGE, DPAGE, or EPAGE signal from the core. Also see
14
0
0
0
6
6
Table 19-22. DBGCBX Field Descriptions
Table 19-21. DBGCA Field Descriptions
Bit 13
MC9S12HZ256 Data Sheet, Rev. 2.05
Bit 5
13
0
0
0
5
5
Bit 12
Bit 4
12
0
0
0
4
4
Description
Description
Table
19-20.
Bit 11
Bit 3
11
0
0
0
3
3
EXTCMP
Bit 10
Bit 2
10
0
0
0
2
2
Freescale Semiconductor
Bit 9
Bit 1
0
0
0
9
1
1
Table
Bit 8
Bit 0
0
0
0
8
0
0
19-20.
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