mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 125

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

4.3.1
Port AD is associated with the analog-to-digital converter (ATD) and keyboard wake-up (KWU)
interrupts. Each pin is assigned to these modules according to the following priority: ATD > KWU >
general-purpose I/O.
For the pins of port AD to be used as inputs, the corresponding bits of the ATDDIEN1 register in the ATD
module must be set to 1 (digital input buffer is enabled). The ATDDIEN1 register does not affect the port
AD pins when they are configured as outputs.
Refer to the ATD block description chapter for information on the ATDDIEN1 register.
During reset, port AD pins are configured as high-impedance analog inputs (digital input buffer is
disabled).
4.3.1.1
Read: Anytime. Write: Anytime.
If the data direction bit of the associated I/O pin (DDRADx) is set to 1 (output), a write to the
corresponding I/O Register bit sets the value to be driven to the Port AD pin. If the data direction bit of the
associated I/O pin (DDRADx) is set to 0 (input), a write to the corresponding I/O Register bit takes place
but has no effect on the Port AD pin.
If the associated data direction bit (DDRADx) is set to 1 (output), a read returns the value of the I/O register
bit.
If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN1 bits is set
to 0 (digital input buffer is disabled), the associated I/O register bit (PTADx) reads “1”.
If the associated data direction bit (DDRADx) is set to 0 (input) and the associated ATDDIEN1 bits is set
to 1 (digital input buffer is enabled), a read returns the value of the pin.
Freescale Semiconductor
KWU:
Reset
ATD:
W
R
KWAD7
PTAD7
Port AD
AN7
Port AD I/O Register (PTAD)
0
7
KWAD6
PTAD6
AN6
0
6
Figure 4-2. Port AD I/O Register (PTAD)
KWAD5
PTAD5
AN55
MC9S12HZ256 Data Sheet, Rev. 2.05
0
5
KWAD4
PTAD4
AN4
0
4
KWAD3
PTAD3
AN3
0
3
Chapter 4 Port Integration Module (PIM9HZ256V2)
KWAD2
PTAD2
AN2
0
2
KWAD1
PTAD1
AN1
0
1
KWAD0
PTAD0
AN0
0
0
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