mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 172

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 5 Clocks and Reset Generator (CRGV4)
5.3.2.1
The SYNR register controls the multiplication factor of the PLL. If the PLL is on, the count in the loop
divider (SYNR) register effectively multiplies up the PLL clock (PLLCLK) from the reference frequency
by 2 x (SYNR+1). PLLCLK will not be below the minimum VCO frequency (f
Read: anytime
Write: anytime except if PLLSEL = 1
172
Reset
ARMCOP
Register
Name
W
R
CRG Synthesizer Register (SYNR)
0
0
7
If PLL is selected (PLLSEL=1), Bus Clock = PLLCLK / 2
Bus Clock must not exceed the maximum operating system frequency.
Write to this register initializes the lock detector bit and the track detector
bit.
W
R
= Unimplemented or Reserved
Bit 7
Bit 7
0
0
0
6
Figure 5-3. CRG Register Summary (continued)
Figure 5-4. CRG Synthesizer Register (SYNR)
= Unimplemented or Reserved
Bit 6
6
0
PLLCLK
SYN5
MC9S12HZ256 Data Sheet, Rev. 2.05
0
5
Bit 5
=
5
0
2xOSCCLKx
SYNR
NOTE
NOTE
0
4
Bit 4
4
0
---------------------------------- -
REFDV
SYNR
SYN3
0
3
Bit 3
+
+
3
0
1
1
SYN2
0
2
Bit 2
2
0
SCM
).
Freescale Semiconductor
SYN1
Bit 1
0
1
1
0
Bit 0
Bit 0
SYN0
0
0
0