mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 367

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Section 12.3.2.1, “MSCAN Control Register 0
point for the recessive bit of the ACK delimiter in the CAN frame. In case of a transmission, the CPU can
only read the time stamp after the respective transmit buffer has been flagged empty.
The timer value, which is used for stamping, is taken from a free running internal CAN bit clock. A timer
overrun is not indicated by the MSCAN. The timer is reset (all bits set to 0) during initialization mode. The
CPU can only read the time stamp registers.
Read: Anytime when TXEx flag is set (see
(CANTFLG)”) and the corresponding transmit buffer is selected in CANTBSEL (see
“MSCAN Transmit Buffer Selection Register
Write: Unimplemented
12.4
12.4.1
This section provides a complete functional description of the MSCAN. It describes each of the features
and modes listed in the introduction.
Freescale Semiconductor
Reset:
Reset:
W
W
Functional Description
R
R
General
TSR15
TSR7
7
x
7
x
Figure 12-34. Time Stamp Register — High Byte (TSRH)
Figure 12-35. Time Stamp Register — Low Byte (TSRL)
TSR14
TSR6
6
x
6
x
MC9S12HZ256 Data Sheet, Rev. 2.05
TSR13
TSR5
5
x
5
x
Section 12.3.2.7, “MSCAN Transmitter Flag Register
(CANTBSEL)”).
(CANCTL0)”). The time stamp is written on the bit sample
TSR12
TSR4
Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
4
x
4
x
TSR11
TSR3
x
x
3
3
TSR10
TSR2
2
x
2
x
TSR9
TSR1
Section 12.3.2.11,
x
x
1
1
TSR8
TSR0
0
x
0
x
367