mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 115
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mc9s12hz256v2
Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12HZ256V2.pdf
(692 pages)
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Chapter 4
Port Integration Module (PIM9HZ256V2)
4.1
The port integration module establishes the interface between the peripheral modules and the I/O pins for
for ports AD, L, M, P, T, U and V.
This section covers:
Each I/O pin can be configured by several registers: input/output selection, drive strength reduction,
enable and select of pull resistors, wired-or mode selection, interrupt enable, and/or status flags.
4.1.1
A standard port has the following minimum features:
Optional features:
Freescale Semiconductor
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Port A, B, E, and K and the BKGD pin, which are shared between the core logic (including
multiplexed bus interface) and the LCD driver
Port AD associated with ATD module (channels 7 through 0) and keyboard wake-up interrupts
Port L connected to the LCD driver and ATD (channels 15 through 8) modules
Port M connected to 2 CAN modules
Port P connected to 1 SCI, 1 IIC and PWM modules
Port S connected to 1 SCI and 1 SPI modules
Port T connected to the timer module (TIM) and the LCD driver
Port U and V associated with PWM motor control and stepper stall detect modules
Input/output selection
5-V output drive with two selectable drive strength (or slew rates)
5-V digital and analog input
Input with selectable pull-up or pull-down device
Open drain for wired-OR connections
Interrupt input with glitch filtering
lntroduction
Features
Ports A, B, E and K, and the BKGD pin are shared between core logic
(including multiplexed bus interface) and the LCD driver. Refer to the
MEBI block description chapter for details on these ports.
MC9S12HZ256 Data Sheet, Rev. 2.05
NOTE
115
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