mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 331
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mc9s12hz256v2
Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12HZ256V2.pdf
(692 pages)
- Current page: 331 of 692
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Freescale Semiconductor
Dummy Read
From IBDR
Switch To
Rx Mode
Y
Byte To IBDR
(Master Rx)
Transmitted
Addr Cycle
Write Next
Last Byte
RXAK=0
End Of
?
?
?
Y
N
N
TX
Stop Signal
Generate
Figure 11-11. Flow-Chart of Typical IIC Interrupt Routine
Y
N
Tx/Rx
Set TXAK =1
?
Y
Byte To Be Read
Byte To Be Read
MC9S12HZ256 Data Sheet, Rev. 2.05
From IBDR
Read Data
And Store
2nd Last
RX
Last
?
?
N
N
Stop Signal
Generate
Y
Y
RTI
Master
Mode
Clear
IBIF
?
Write Data
To IBDR
(Read)
Set TX
Mode
N
N
Y
Dummy Read
From IBDR
Clear IBAL
IAAS=1
Set RX
SRW=1
Mode
Y
?
?
Chapter 11 Inter-Integrated Circuit (IICV2)
N
Address Transfer
(Write)
Tx Next
Byte
Y
Y
Y
Dummy Read
From IBDR
Arbitration
ACK From
Switch To
Receiver
IAAS=1
Rx Mode
TX/RX
Lost
?
?
?
?
N
N
N
TX
Data Transfer
From IBDR
Read Data
And Store
RX
331
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