mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 77

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

2.3.2.15
This register is reserved for factory testing and is not accessible.
All bits read 0 and are not writable.
2.4
2.4.1
Write and read operations are both used for the program, erase, erase verify, and data compress algorithms
described in this subsection. The program and erase algorithms are time controlled by a state machine
whose timebase, FCLK, is derived from the oscillator clock via a programmable divider. The command
register as well as the associated address and data registers operate as a buffer and a register (2-stage FIFO)
so that a second command along with the necessary data and address can be stored to the buffer while the
first command remains in progress. This pipelined operation allows a time optimization when
programming more than one word on a specific row in the Flash block as the high voltage generation can
be kept active in between two programming commands. The pipelined operation also allows a
simplification of command launching. Buffer empty as well as command completion are signalled by flags
in the Flash status register with interrupts generated, if enabled.
The next paragraphs describe:
2.4.1.1
Prior to issuing any program, erase, erase verify, or data compress command, it is first necessary to write
the FCLKDIV register to divide the oscillator clock down to within the 150 kHz to 200 kHz range.
Because the program and erase timings are also a function of the bus clock, the FCLKDIV determination
must take this information into account.
If we define:
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1. How to write the FCLKDIV register.
2. Command write sequences used to program, erase, and verify the Flash memory.
3. Valid Flash commands.
4. Effects resulting from illegal Flash command write sequences or aborting Flash operations.
•
•
W
R
FCLK as the clock of the Flash timing control block,
Tbus as the period of the bus clock, and
Functional Description
Flash Command Operations
RESERVED4
Writing the FCLKDIV Register
7
0
0
= Unimplemented or Reserved
6
0
0
MC9S12HZ256 Data Sheet, Rev. 2.05
5
0
0
Figure 2-21. RESERVED4
4
0
0
3
0
0
Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
2
0
0
1
0
0
0
0
0
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