mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 493

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

For the description of PACLK please refer
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an
input clock to the timer counter. The change from one selected clock to the other happens immediately
after these bits are written.
Freescale Semiconductor
PAOVI
Field
PAI
1
0
Pulse Accumulator Overflow Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAOVF is set.
Pulse Accumulator Input Interrupt Enable
0 Interrupt inhibited.
1 Interrupt requested if PAIF is set.
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
because the 64 clock is generated by the timer prescaler.
PAMOD
CLK1
0
0
1
1
0
0
1
1
Table 16-17. PACTL Field Descriptions (continued)
PEDGE
CLK0
0
1
0
1
0
1
0
1
Table 16-19. Timer Clock Selection
MC9S12HZ256 Data Sheet, Rev. 2.05
Table 16-18. Pin Action
Use PACLK/65536 as timer counter clock frequency
Use PACLK/256 as timer counter clock frequency
Figure
Use timer prescaler clock as timer counter clock
Div. by 64 clock enabled with pin high level
Use PACLK as input to timer counter clock
Div. by 64 clock enabled with pin low level
NOTE
16-24.
Description
Timer Clock
Falling edge
Rising edge
Pin Action
Chapter 16 Timer Module (TIM16B8CV1)
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