mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 78

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 2 256 Kbyte Flash Module (FTS256K2V1)
Then, FCLKDIV register bits PRDIV8 and FDIV[5:0] are to be set as described in
For example, if the oscillator clock frequency is 950 kHz and the bus clock frequency is 10 MHz,
FCLKDIV bits FDIV[5:0] must be set to 4 (000100) and bit PRDIV8 set to 0. The resulting FCLK
frequency is then 190 kHz. As a result, the Flash program and erase algorithm timings are increased over
the optimum target by:
If the FCLKDIV register is written, the FDIVLD bit is set automatically. If the FDIVLD bit is 0, the
FCLKDIV register has not been written since the last reset. Flash commands will not be executed if the
FCLKDIV register has not been written to.
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INT(x) as taking the integer part of x (e.g. INT(4.323)=4).
Program and erase command execution time will increase proportionally
with the period of FCLK. Because of the impact of clock synchronization
on the accuracy of the functional timings, programming or erasing the Flash
memory cannot be performed if the bus clock runs at less than 1 MHz.
Programming or erasing the Flash memory with FCLK < 150 kHz must be
avoided. Setting FCLKDIV to a value such that FCLK < 150 kHz can
destroy the Flash memory due to overstress. Setting FCLKDIV to a value
such that (1/FCLK + Tbus) < 5 s can result in incomplete programming or
erasure of the Flash memory cells.
MC9S12HZ256 Data Sheet, Rev. 2.05
200 190
–
CAUTION
200 100
=
5%
Figure
Freescale Semiconductor
2-22.