mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 356

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mc9s12hz256v2

Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
Module Base + 0x0018 (CANIDAR4)
Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
356
AC[7:0]
Figure 12-18. MSCAN Identifier Acceptance Registers (Second Bank) — CANIDAR4–CANIDAR7
Field
7:0
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
0x0019 (CANIDAR5)
0x001A (CANIDAR6)
0x001B (CANIDAR7)
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
AC7
AC7
AC7
AC7
0
0
0
0
7
7
7
7
Table 12-22. CANIDAR4–CANIDAR7 Register Field Descriptions
AC6
AC6
AC6
AC6
6
0
6
0
6
0
6
0
MC9S12HZ256 Data Sheet, Rev. 2.05
AC5
AC5
AC5
AC5
0
0
0
0
5
5
5
5
AC4
AC4
AC4
AC4
4
0
4
0
4
0
4
0
Description
AC3
AC3
AC3
AC3
0
0
0
0
3
3
3
3
AC2
AC2
AC2
AC2
2
0
2
0
2
0
2
0
Freescale Semiconductor
AC1
AC1
AC1
AC1
0
0
0
0
1
1
1
1
AC0
AC0
AC0
AC0
0
0
0
0
0
0
0
0

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