mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 38

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 1 MC9S12HZ256 Device Overview
1.5.3
This pin is reserved for test.
1.5.4
Dedicated pin used to create the PLL loop filter. Please ask your Freescale representative for the
interactive application note to compute PLL loop filter elements. Any current leakage on this pin must be
avoided.
1.5.5
The BKGD/TAGHI/MODC pin is used as a pseudo-open-drain pin for the background debug
communication. In MCU expanded modes of operation when instruction tagging is on, an input low on
this pin during the falling edge of E-clock tags the high half of the instruction word being read into the
instruction queue. It is used as a MCU operating mode select pin during reset. The state of this pin is
latched to the MODC bit at the rising edge of RESET.
1.5.6
1.5.6.1
PAD7–PAD0 are general-purpose input or output pins and analog inputs for the analog-to-digital
converter. They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode.
1.5.6.2
PA7–PA0 are general-purpose input or output pins. They can be configured as frontplane segment driver
outputs FP15–FP8 of the LCD. In MCU expanded modes of operation, these pins are used for the
multiplexed external address and data bus.
38
TEST — Test Pin
XFC — PLL Loop Filter Pin
BKGD / TAGHI / MODC — Background Debug, Tag High, and Mode
Pin
Port Pins
PAD[7:0] / AN[7:0] / KWAD[7:0] — Port AD I/O Pins [7:0]
PA[7:0] / FP[15:8] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
The TEST pin must be tied to V
Figure 1-9. PLL Loop Filter Connections
MC9S12HZ256 Data Sheet, Rev. 2.05
MCU
XFC
SS
NOTE
in all applications.
V
DDPLL
R
C
S
V
DDPLL
C
P
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