mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 355

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Module Base + 0x0010 (CANIDAR0)
12.3.2.16 MSCAN Identifier Acceptance Registers (CANIDAR0-7)
On reception, each message is written into the background receive buffer. The CPU is only signalled to
read the message if it passes the criteria in the identifier acceptance and identifier mask registers
(accepted); otherwise, the message is overwritten by the next message (dropped).
The acceptance registers of the MSCAN are applied on the IDR0–IDR3 registers (see
“Identifier Registers
“Identifier Acceptance
For extended identifiers, all four acceptance and mask registers are applied. For standard identifiers, only
the first two (CANIDAR0/1, CANIDMR0/1) are applied.
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Freescale Semiconductor
AC[7:0]
Field
7:0
Figure 12-17. MSCAN Identifier Acceptance Registers (First Bank) — CANIDAR0–CANIDAR3
Reset
Reset
Reset
Reset
W
W
W
W
R
R
R
R
0x0011 (CANIDAR1)
0x0012 (CANIDAR2)
0x0013 (CANIDAR3)
Acceptance Code Bits — AC[7:0] comprise a user-defined sequence of bits with which the corresponding bits
of the related identifier register (IDRn) of the receive message buffer are compared. The result of this comparison
is then masked with the corresponding identifier mask register.
AC7
AC7
AC7
AC7
0
0
0
0
7
7
7
7
(IDR0–IDR3)”) of incoming messages in a bit by bit manner (see
Table 12-21. CANIDAR0–CANIDAR3 Register Field Descriptions
Filter”).
AC6
AC6
AC6
AC6
6
0
6
0
6
0
6
0
MC9S12HZ256 Data Sheet, Rev. 2.05
AC5
AC5
AC5
AC5
0
0
0
0
5
5
5
5
Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
AC4
AC4
AC4
AC4
4
0
4
0
4
0
4
0
Description
AC3
AC3
AC3
AC3
0
0
0
0
3
3
3
3
AC2
AC2
AC2
AC2
2
0
2
0
2
0
2
0
AC1
AC1
AC1
AC1
Section 12.3.3.1,
Section 12.4.3,
0
0
0
0
1
1
1
1
AC0
AC0
AC0
AC0
0
0
0
0
0
0
0
0
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