mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 544

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 19 Debug Module (DBGV1)
19.3.2.2
544
Reset
Field
TRG
CF
3:0
AF
BF
7
6
5
W
R
Trigger A Match Flag — The AF bit indicates if trigger A match condition was met since arming. This bit is
cleared when ARM in DBGC1 is written to a 1 or on any write to this register.
0 Trigger A did not match
1 Trigger A match
Trigger B Match Flag — The BF bit indicates if trigger B match condition was met since arming.This bit is
cleared when ARM in DBGC1 is written to a 1 or on any write to this register.
0 Trigger B did not match
1 Trigger B match
Comparator C Match Flag — The CF bit indicates if comparator C match condition was met since arming.This
bit is cleared when ARM in DBGC1 is written to a 1 or on any write to this register.
0 Comparator C did not match
1 Comparator C match
Trigger Mode Bits — The TRG bits select the trigger mode of the DBG module as shown
Section 19.4.2.5, “Trigger
AF
Debug Status and Control Register (DBGSC)
0
7
= Unimplemented or Reserved
Figure 19-5. Debug Status and Control Register (DBGSC)
BF
0
6
TRG Value
Table 19-5. DBGSC Field Descriptions
Modes,” for more detail.
Table 19-6. Trigger Mode Encoding
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1111
MC9S12HZ256 Data Sheet, Rev. 2.05
CF
0
5
0
0
4
A and Not B (full mode)
Description
A then event only B
A and B (full mode)
(Defaults to A only)
Outside range
Event only B
Inside range
Reserved
Meaning
A then B
A only
A or B
0
3
0
2
TRG
Freescale Semiconductor
0
1
Table
19-6. See
0
0