mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 344

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
The bit time is determined by the oscillator frequency, the baud rate prescaler, and the number of time
quanta (Tq) clock cycles per bit (as shown in
12.3.2.5
A flag can be cleared only by software (writing a 1 to the corresponding bit position) when the condition
which caused the setting is no longer valid. Every flag has an associated interrupt enable bit in the
CANRIER register.
Read: Anytime
Write: Anytime when out of initialization mode, except RSTAT[1:0] and TSTAT[1:0] flags which are
read-only; write of 1 clears flag; write of 0 is ignored.
1. The RSTAT[1:0], TSTAT[1:0] bits are not affected by initialization mode.
344
Reset:
W
R
1
MSCAN Receiver Flag Register (CANRFLG)
WUPIF
The CANRFLG register is held in the reset state
mode is active (INITRQ = 1 and INITAK = 1). This register is writable again
as soon as the initialization mode is exited (INITRQ = 0 and INITAK = 0).
This setting is not valid. Please refer to
TSEG13
Bit Time
0
7
0
0
0
0
1
1
:
Figure 12-6. MSCAN Receiver Flag Register (CANRFLG)
= Unimplemented
CSCIF
=
6
0
TSEG12
----------------------------------------------------- -
Prescaler value
0
0
0
0
1
1
:
f CANCLK
Table 12-10. Time Segment 1 Values
MC9S12HZ256 Data Sheet, Rev. 2.05
RSTAT1
0
5
TSEG11
0
0
1
1
1
1
:
Table 12-9
Table 12-36
NOTE
RSTAT0
4
0
1
TSEG10
+
and
TimeSegment1
0
1
0
1
0
1
:
for valid settings.
TSTAT1
Table
1
0
3
when the initialization
12-10).
15 Tq clock cycles
16 Tq clock cycles
2 Tq clock cycles
3 Tq clock cycles
Time segment 1
1 Tq clock cycle
4 Tq clock cycles
TSTAT0
2
0
+
TimeSegment2
:
Freescale Semiconductor
1
OVRIF
1
1
0
1
Eqn. 12-1
RXF
0
0