mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 132
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mc9s12hz256v2
Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12HZ256V2.pdf
(692 pages)
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Chapter 4 Port Integration Module (PIM9HZ256V2)
4.3.2.4
Read: Anytime. Write: Anytime.
This register configures the drive strength of configured output pins as either full or reduced. If a pin is
configured as input, the corresponding Reduced Drive Register bit has no effect.
4.3.2.5
Read:Anytime. Write:Anytime.
This register configures whether a pull-up or a pull-down device is activated on configured input pins. If
a pin is configured as output, the corresponding Pull Device Enable Register bit has no effect.
132
RDRL[7:0]
PERL[7:0]
Reset
Reset
Field
Field
7:0
7:0
W
W
R
R
RDRL7
PERL7
Reduced Drive Port L
0 Full drive strength at output.
1 Associated pin drives at about 1/3 of the full drive strength.
Pull Device Enable Port L
0 Pull-up or pull-down device is disabled.
1 Pull-up or pull-down device is enabled.
Port L Reduced Drive Register (RDRL)
Port L Pull Device Enable Register (PERL)
0
1
7
7
RDRL6
PERL6
Figure 4-14. Port L Pull Device Enable Register (PERL)
0
1
6
6
Figure 4-13. Port L Reduced Drive Register (RDRL)
Table 4-10. RDRL Field Descriptions
Table 4-11. PERL Field Descriptions
RDRL5
PERL5
MC9S12HZ256 Data Sheet, Rev. 2.05
0
1
5
5
RDRL4
PERL4
0
1
4
4
Description
Description
RDRL3
PERL3
0
1
3
3
RDRL2
PERL2
0
1
2
2
RDRL1
PERL1
Freescale Semiconductor
0
1
1
1
RDRL0
PERL0
0
1
0
0
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