mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 495
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mc9s12hz256v2
Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12HZ256V2.pdf
(692 pages)
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16.3.2.17 Pulse Accumulators Count Registers (PACNT)
Read: Anytime
Write: Anytime
These registers contain the number of active input edges on its input pin since the last reset.
When PACNT overflows from 0xFFFF to 0x0000, the Interrupt flag PAOVF in PAFLG (0x0021) is set.
Full count register access should take place in one clock cycle. A separate read/write for high byte and low
byte will give a different result than accessing them as a word.
16.4
This section provides a complete functional description of the timer TIM16B8C block. Please refer to the
detailed timer block diagram in
Freescale Semiconductor
Reset
Reset
W
W
R
R
Functional Description
PACNT15
PACNT7
15
0
0
7
edge on the pulse accumulator input pin may miss the last count because the
input has to be synchronized with the bus clock first.
Reading the pulse accumulator counter registers immediately after an active
Figure 16-26. Pulse Accumulator Count Register High (PACNTH)
Figure 16-27. Pulse Accumulator Count Register Low (PACNTL)
PACNT14
PACNT6
14
0
0
6
Figure 16-28
PACNT13
PACNT5
MC9S12HZ256 Data Sheet, Rev. 2.05
13
0
0
5
as necessary.
PACNT12
PACNT4
NOTE
12
0
0
4
PACNT11
PACNT3
11
0
0
3
PACNT10
PACNT2
Chapter 16 Timer Module (TIM16B8CV1)
10
0
0
2
PACNT9
PACNT1
0
0
9
1
PACNT8
PACNT0
0
0
0
0
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