mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 298

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 10 Stepper Stall Detector (SSDV1)
10.3.2.3
Read: anytime
Write: anytime
298
l
SSDWAI
SDCPU
Reset
MCEN
AOVIE
FLMC
RTZE
Field
Field
3
2
0
7
6
5
W
R
RTZE
Force Load Register into the Modulus Counter Count Register — This bit always reads zero.
0 Write zero to this bit has no effect.
1 Write one into this bit loads the load register into the modulus counter count register.
Modulus Down-Counter Enable
0 Modulus down-counter is disabled. The modulus counter (MDCCNT) is preset to 0xFFFF. This will prevent an
1 Modulus down-counter is enabled.
Accumulator Overflow Interrupt Enable
0 Interrupt disabled.
1 Interrupt enabled. An interrupt will be generated when the accumulator overflow interrupt flag (AOVIF) is set.
Return to Zero Enable — If this bit is set, the coils are controlled by the SSD and are configured into one of the
four full step states as shown in
0 RTZ is disabled.
1 RTZ is enabled.
Sigma-Delta Converter Power Up — This bit provides on/off control for the sigma-delta converter allowing
reduced MCU power consumption. Because the analog circuit is turned off when powered down, the sigma-delta
converter requires a recovery time after it is powered up.
0 Sigma-delta converter is powered down.
1 Sigma-delta converter is powered up.
SSD Disabled during Wait Mode — When entering Wait Mode, this bit provides on/off control over the SSD
allowing reduced MCU power consumption. Because the analog circuit is turned off when powered down, the
sigma-delta converter requires a recovery time after exit from Wait Mode.
0 SSD continues to run in WAIT mode.
1 Entering WAIT mode freezes the clock to the prescaler divider, powers down the sigma-delta converter, and
Stepper Stall Detector Control Register (SSDCTL)
0
7
early interrupt flag when the modulus down-counter is enabled.
if RTZE bit is set, the sine and cosine coils are recirculated via VSSM.
= Unimplemented or Reserved
Figure 10-4. Stepper Stall Detector Control Register (SSDCTL)
SDCPU
0
6
Table 10-7. MDCCTL Field Descriptions (continued)
Table 10-8. SSDCTL Field Descriptions
SSDWAI
MC9S12HZ256 Data Sheet, Rev. 2.05
0
5
Table
10-6. If this bit is cleared, the coils are not controlled by the SSD.
FTST
0
4
Description
Description
0
0
3
0
0
2
Freescale Semiconductor
0
1
ACLKS
0
0