mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 157

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

4.3.8.2
Read: Anytime. Write: Never, writes to this register have no effect.
If the associated slew rate control is enabled (digital input buffer is disabled), a read returns a “1”. If the
associated slew rate control is disabled (digital input buffer is enabled), a read returns the status of the
associated pin.
4.3.8.3
Read: Anytime. Write: Anytime.
This register configures port pins PV[7:0] as either input or output.
When enabled, the SSD or MC modules force the I/O state to be an output for each associated pin and the
associated Data Direction Register bit has no effect. If the SSD and MC modules are disabled, the
corresponding Data Direction Register bits revert to control the I/O direction of the associated pins.
Freescale Semiconductor
DDRV[7:0]
Reset
Reset
Field
7:0
W
W
R
R
DDRV7
PTIV7
Data Direction Port V
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Port V Input Register (PTIV)
Port V Data Direction Register (DDRV)
u
0
7
7
= Reserved or Unimplemented
DDRV6
PTIV6
u
0
6
6
Figure 4-51. Port V Data Direction Register (DDRV)
Figure 4-50. Port V Input Register (PTIV)
Table 4-36. DDRV Field Descriptions
DDRV5
PTIV5
MC9S12HZ256 Data Sheet, Rev. 2.05
u
0
5
5
DDRV4
PTIV4
u
0
4
4
Description
u = Unaffected by reset
DDRV3
PTIV3
u
0
3
3
Chapter 4 Port Integration Module (PIM9HZ256V2)
DDRV2
PTIV2
u
0
2
2
DDRV1
PTIV1
u
0
1
1
DDRV0
PTIV0
u
0
0
0
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