mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 357
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mc9s12hz256v2
Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12HZ256V2.pdf
(692 pages)
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Module Base + 0x0014 (CANIDMR0)
12.3.2.17 MSCAN Identifier Mask Registers (CANIDMR0–CANIDMR7)
The identifier mask register specifies which of the corresponding bits in the identifier acceptance register
are relevant for acceptance filtering. To receive standard identifiers in 32 bit filter mode, it is required to
program the last three bits (AM[2:0]) in the mask registers CANIDMR1 and CANIDMR5 to “don’t care.”
To receive standard identifiers in 16 bit filter mode, it is required to program the last three bits (AM[2:0])
in the mask registers CANIDMR1, CANIDMR3, CANIDMR5, and CANIDMR7 to “don’t care.”
Read: Anytime
Write: Anytime in initialization mode (INITRQ = 1 and INITAK = 1)
Freescale Semiconductor
AM[7:0]
Field
7:0
Reset
Reset
Reset
Reset
Figure 12-19. MSCAN Identifier Mask Registers (First Bank) — CANIDMR0–CANIDMR3
W
W
W
W
R
R
R
R
0x0015 (CANIDMR1)
0x0016 (CANIDMR2)
0x0017 (CANIDMR3)
Acceptance Mask Bits — If a particular bit in this register is cleared, this indicates that the corresponding bit in
the identifier acceptance register must be the same as its identifier bit before a match is detected. The message
is accepted if all such bits match. If a bit is set, it indicates that the state of the corresponding bit in the identifier
acceptance register does not affect whether or not the message is accepted.
0 Match corresponding acceptance code register and identifier bits
1 Ignore corresponding acceptance code register bit
AM7
AM7
AM7
AM7
0
0
0
0
7
7
7
7
Table 12-23. CANIDMR0–CANIDMR3 Register Field Descriptions
AM6
AM6
AM6
AM6
6
0
6
0
6
0
6
0
MC9S12HZ256 Data Sheet, Rev. 2.05
AM5
AM5
AM5
AM5
0
0
0
0
5
5
5
5
Chapter 12 Freescale’s Scalable Controller Area Network (MSCANV2)
AM4
AM4
AM4
AM4
4
0
4
0
4
0
4
0
Description
AM3
AM3
AM3
AM3
0
0
0
0
3
3
3
3
AM2
AM2
AM2
AM2
2
0
2
0
2
0
2
0
AM1
AM1
AM1
AM1
0
0
0
0
1
1
1
1
AM0
AM0
AM0
AM0
0
0
0
0
0
0
0
0
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