mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 182

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

Chapter 5 Clocks and Reset Generator (CRGV4)
5.3.2.12
This register is used to restart the COP time-out period.
Read: always reads 0x0000
Write: anytime
When the COP is disabled (CR[2:0] = “000”) writing to this register has no effect.
When the COP is enabled by setting CR[2:0] nonzero, the following applies:
5.4
This section gives detailed informations on the internal operation of the design.
5.4.1
The PLL is used to run the MCU from a different time base than the incoming OSCCLK. For increased
flexibility, OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency. This offers
a finer multiplication granularity. The PLL can multiply this reference clock by a multiple of 2, 4, 6,...
126,128 based on the SYNR register.
The PLL is a frequency generator that operates in either acquisition mode or tracking mode, depending on
the difference between the output frequency and the target frequency. The PLL can change between
acquisition and tracking modes either automatically or manually.
182
Reset
W
R
Writing any value other than 0x0055 or 0x00AA causes a COP reset. To restart the COP time-out
period you must write 0x0055 followed by a write of 0x00AA. Other instructions may be executed
between these writes but the sequence (0x0055, 0x00AA) must be completed prior to COP end of
time-out period to avoid a COP reset. Sequences of 0x0055 writes or sequences of 0x00AA writes
are allowed. When the WCOP bit is set, 0x0055 and 0x00AA writes must be done in the last 25%
of the selected time-out period; writing any value in the first 75% of the selected period will cause
a COP reset.
Functional Description
Phase Locked Loop (PLL)
Bit 7
CRG COP Timer Arm/Reset Register (ARMCOP)
0
0
7
Although it is possible to set the two dividers to command a very high clock
frequency, do not exceed the specified bus frequency limit for the MCU.
If (PLLSEL = 1), Bus Clock = PLLCLK / 2
Bit 6
0
0
6
PLLCLK
Figure 5-15. ARMCOP Register Diagram
MC9S12HZ256 Data Sheet, Rev. 2.05
Bit 5
0
0
5
=
2 OSCCLK
CAUTION
Bit 4
0
0
4
---------------------------------- -
REFDV
SYNR
Bit 3
0
0
3
+
+
1
1
Bit 2
0
0
2
Freescale Semiconductor
Bit 1
0
0
1
Bit 0
0
0
0