mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 153

• Manufacturer Part Number: mc9s12hz256v2
• Description: Hcs12 Microcontrollers
• Manufacturer: Freescale Semiconductor, Inc

4.3.7.2
Read: Anytime. Write: Never, writes to this register have no effect.
If the associated slew rate control is enabled (digital input buffer is disabled), a read returns a “1”. If the
associated slew rate control is disabled (digital input buffer is enabled), a read returns the status of the
associated pin.
4.3.7.3
Read: Anytime. Write: Anytime.
This register configures port pins PU[7:0] as either input or output.
When enabled, the SSD or MC modules force the I/O state to be an output for each associated pin and the
associated Data Direction Register bit has no effect. If the SSD and MC modules are disabled, the
corresponding Data Direction Register bits revert to control the I/O direction of the associated pins.
Freescale Semiconductor
DDRU[7:0]
Reset
Reset
Field
7:0
W
W
R
R
DDRU7
PTIU7
Data Direction Port U
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Port U Input Register (PTIU)
Port U Data Direction Register (DDRU)
u
0
7
7
= Reserved or Unimplemented
DDRU6
PTIU6
u
0
6
6
Figure 4-45. Port U Data Direction Register (DDRU)
Figure 4-44. Port U Input Register (PTIU)
Table 4-32. DDRU Field Descriptions
DDRU5
PTIU5
MC9S12HZ256 Data Sheet, Rev. 2.05
u
0
5
5
DDRU4
PTIU4
u
0
4
4
Description
u = Unaffected by reset
DDRU3
PTIU3
u
0
3
3
Chapter 4 Port Integration Module (PIM9HZ256V2)
DDRU2
PTIU2
u
0
2
2
DDRU1
PTIU1
u
0
1
1
DDRU0
PTIU0
u
0
0
0
153