mc9s12hz256v2 Freescale Semiconductor, Inc, mc9s12hz256v2 Datasheet - Page 284
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mc9s12hz256v2
Manufacturer Part Number
mc9s12hz256v2
Description
Hcs12 Microcontrollers
Manufacturer
Freescale Semiconductor, Inc
Datasheet
1.MC9S12HZ256V2.pdf
(692 pages)
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Chapter 9 Motor Controller (MC10B8CV1)
The motor controller channel frequency of operation can be calculated using the following formula if
DITH = 1:
Table 9-13
different peripheral bus clock frequencies and the prescaler value.
9.4.4
In order to prevent large peak current draw from the motor power supply, selectable delays can be used to
stagger the high logic level to low logic level transitions on the motor controller outputs. The timing delay,
t
selectable between 0, 1, 2, or 3 motor controller timer counter clock cycles.
284
d
, is determined by the CD[1:0] bits in the corresponding channel control register (MCMCx) and is
shows examples of the motor controller channel frequencies that can be generated based on
Output Switching Delay
Both equations are only valid if MCPER is not equal to 0. M = 1 for left or
right aligned mode, M = 2 for center aligned mode.
Due to the selectable slew rate control of the outputs, clipping may occur on
short output pulses.
A PWM channel gets disabled at the next timer counter overflow without
notice of the switching delay.
Prescaler
Motor Channel Frequency (Hz)
1/2
1/4
1/8
1
Table 9-13. Motor Controller Channel Frequencies (Hz),
MCPER = 256, DITH = 0, MCAM = 10, 01
16 MHz
62500
31250
15625
7813
MC9S12HZ256 Data Sheet, Rev. 2.05
Peripheral Bus Clock Frequency
10 MHz
39063
19531
9766
4883
NOTE
NOTE
NOTE
=
------------------------------------- -
MCPER M 2
8 MHz
31250
15625
7813
3906
f
TC
5 MHz
19531
9766
4883
2441
4 MHz
15625
7813
3906
1953
Freescale Semiconductor
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