DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 102

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

5.4.2
The interrupt priority is predetermined. When multiple interrupts occur simultaneously
(overlapped interruptions), the interrupt controller (INTC) determines their relative priorities and
starts the exception handling according to the results.
The priority of interrupts is expressed as priority levels 0 to 16, with priority 0 the lowest and
priority 16 the highest. The NMI interrupt has priority 16 and cannot be masked, so it is always
accepted. The priority level of the user break interrupt is 15. IRQ interrupt and on-chip peripheral
module interrupt priority levels can be set freely using the interrupt priority registers A to F and H
to M (IPRA to IPRF and IPRH to IPRM) of the INTC as shown in table 5.8. The priority levels
that can be set are 0 to 15. Level 16 cannot be set. For details on IPRA to IPRF, see section 6.3.4,
Interrupt Priority Registers A to F and H to M (IPRA to IPRF and IPRH to IPRM).
Table 5.8
Note:
5.4.3
When an interrupt occurs, the interrupt controller (INTC) ascertains its priority level. NMI is
always accepted, but other interrupts are only accepted if they have a priority level higher than the
priority level set in the interrupt mask bits (I3 to I0) of the status register (SR).
When an interrupt is accepted, exception handling begins. In interrupt exception handling, the
CPU saves SR and the program counter (PC) to the stack. The priority level of the accepted
interrupt is written to bits I3 to I0 in SR. Although the priority level of the NMI is 16, the value set
in bits I3 to I0 is H'F (level 15). Next, the start address of the exception handling routine is fetched
from the exception handling vector table for the accepted interrupt, and program execution
branches to that address and the program starts. For details on the interrupt exception handling, see
section 6.6, Interrupt Operation.
Rev. 5.00 Mar. 06, 2009 Page 82 of 770
REJ09B0243-0500
Type
NMI
User break*
IRQ
On-chip peripheral module
* The user break interrupt is not generated on the 32 Kbyte (SH71251A and SH71241A)
Interrupt Priority
Interrupt Exception Handling
and 16 Kbyte (SH71250A and SH71240A) versions.
Interrupt Priority
Priority Level
16
15
0 to 15
Comment
Fixed priority level. Cannot be masked.
Fixed priority level. Can be masked.
Set with interrupt priority registers A to F and H
to M (IPRA to IPRF and IPRH to IPRM).