DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 39

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.2.1
There are sixteen 32-bit general registers (Rn), designated R0 to R15. The general registers are
used for data processing and address calculation. R0 is also used as an index register. With a
number of instructions, R0 is the only register that can be used. R15 is used as a hardware stack
pointer (SP). In exception handling, R15 is used for accessing the stack to save or restore the
status register (SR) and program counter (PC) values.
2.2.2
There are three 32-bit control registers, designated status register (SR), global base register
(GBR), and vector base register (VBR). SR indicates a processing state. GBR is used as a base
address in GBR indirect addressing mode for data transfer of on-chip peripheral module registers.
VBR is used as a base address of the exception handling (including interrupts) vector table.
• Status register (SR)
Initial value:
Initial value:
Bit
31 to 10
9
8
7 to 4
3, 2
R/W:
R/W:
Bit:
Bit:
General Registers (Rn)
Control Registers
31
15
R
R
0
0
-
-
Bit
name
⎯
M
Q
I[3:0]
⎯
30
14
R
R
0
0
-
-
Default
All 0
Undefined
Undefined
1111
All 0
29
13
R
R
0
0
-
-
28
12
R
R
0
0
-
-
27
11
R
R
0
0
-
-
Read/
Write
R
R/W
R/W
R/W
R
26
10
R
R
0
0
-
-
R/W
25
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Used by the DIV0U, DIV0S, and DIV1 instructions.
Used by the DIV0U, DIV0S, and DIV1 instructions.
Interrupt Mask
Reserved
These bits are always read as 0. The write value
should always be 0.
R
M
0
9
-
-
R/W
24
R
Q
0
8
-
-
R/W
23
R
0
7
1
-
R/W
22
R
0
6
1
-
Rev. 5.00 Mar. 06, 2009 Page 19 of 770
I[3:0]
R/W
21
R
0
5
1
-
R/W
20
R
0
4
1
-
19
R
R
0
3
0
-
-
REJ09B0243-0500
18
R
R
0
2
0
-
-
R/W
17
R
0
1
S
-
-
R/W
16
R
0
0
T
-
-