DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 473

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Receiving Serial Data (Asynchronous Mode):
Figure 12.6 shows a sample flowchart for serial reception.
Use the following procedure for serial data reception after enabling the SCI for reception.
No
No
Read ORER, PER, and FER
Read RDRF flag in SCSSR
Clear RE bit in SCSCR to 0
PER, FER, or ORER = 1?
SCRDR, and clear RDRF
Figure 12.6 Sample Flowchart for Receiving Serial Data
Read receive data in
flag in SCSSR to 0
All data received?
Start of reception
End of reception
flags in SCSSR
RDRF = 1?
No
Yes
Yes
Error handling
Yes
[1] Receive error handling and break
[2] SCI status check and receive data read:
[3] Serial reception continuation procedure:
detection:
PER, and FER flags in SCSSR to identify
the error. After performing the
appropriate error processing, ensure that
the ORER, PER, and FER flags are all
cleared to 0. Reception cannot be
resumed if any of these flags are set to 1.
In the case of a framing error, a break
can also be detected by reading the
value of the RXD pin.
then read the receive data in SCRDR
clear the RDRF flag to 0.
RDRF flag to 0 before the stop bit for the
current frame is received.
If a receive error occurs, read the ORER,
Read SCSSR and check that RDRF = 1,
To continue serial reception, clear the
Rev. 5.00 Mar. 06, 2009 Page 453 of 770
REJ09B0243-0500