DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 331

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2. Basic Operation Example of A/D Converter Start Request Delaying Function
3. Buffer Transfer
4. A/D Converter Start Request Delaying Function Linked with Interrupt Skipping
Figure 9.74 Basic Example of A/D Converter Start Request Signal (TRG4AN) Operation
A/D converter start request
Figure 9.74 shows a basic example of A/D converter request signal (TRG4AN) operation
when the trough of TCNT_4 is specified for the buffer transfer timing and an A/D converter
start request signal is output during TCNT_4 down-counting.
The data in the timer A/D converter start request cycle set registers (TADCORA_4 and
TADCORB_4) is updated by writing data to the timer A/D converter start request cycle set
buffer registers (TADCOBRA_4 and TADCOBRB_4). Data is transferred from the buffer
registers to the respective cycle set registers at the timing selected with the BF1 and BF0 bits
in the timer A/D converter start request control register (TADCR_4).
A/D converter start requests (TRG4AN and TRG4BN) can be issued in coordination with
interrupt skipping by making settings in the ITA3AE, ITA4VE, ITB3AE, and ITB4VE bits in
the timer A/D converter start request control register (TADCR).
Figure 9.75 shows an example of A/D converter start request signal (TRG4AN) operation
when TRG4AN output is enabled during TCNT_4 up-counting and down-counting and A/D
converter start requests are linked with interrupt skipping.
Figure 9.76 shows another example of A/D converter start request signal (TRG4AN) operation
when TRG4AN output is enabled during TCNT_4 up-counting and A/D converter start
requests are linked with interrupt skipping.
TADCOBRA_4
TADCORA_4
Transfer from cycle buffer
register to cycle register
(TRG4AN)
Transfer from cycle buffer
register to cycle register
TCNT_4
Rev. 5.00 Mar. 06, 2009 Page 311 of 770
Transfer from cycle buffer
register to cycle register
(Complementary PWM mode)
REJ09B0243-0500