DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 178

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Figure 9.1 shows a block diagram of the MTU2.
Rev. 5.00 Mar. 06, 2009 Page 158 of 770
REJ09B0243-0500
Internal clock:
External clock: TCLKA
Channel 3: TIOC3A
Channel 4: TIOC4A
Channel 0: TIOC0A
Channel 1: TIOC1A
Channel 2: TIOC2A
Channel 5: TIC5U
Input/output pins
Input/output pins
Clock input
Input pins
MPφ/1024
TSTR: Timer start register
TSYR: Timer synchronous register
TCR:
TMDR: Timer mode register
TIOR:
TIORH: Timer I/O control register H
TIORL: Timer I/O control register L
TIER:
TGCR: Timer gate control register
TOER: Timer output master enable register
TOCR: Timer output control register
TSR:
TCNT: Timer counter
TCNTS: Timer subcounter
[Legend]
Note: * Supported only by the SH7125.
MPφ/256
TIOC3C
TIOC3D
TIOC4C
TIOC4D
TIOC3B
TIOC4B
TIOC0B
TIOC0C
TIOC0D
TIOC1B
TIOC2B
MPφ/16
MPφ/64
TIC5W
TCLKB
TCLKC
TCLKD
TIC5V
MPφ/1
MPφ/4
Timer control register
Timer I/O control register
Timer interrupt enable register
Timer status register
*
*
*
*
Figure 9.1 Block Diagram of MTU2
TCDR:
TCBR:
TDDR:
TGRA:
TGRB:
TGRC:
TGRD:
TGRE:
TGRF:
TGRU:
TGRV:
TGRW: Timer general register W
Timer cycle data register
Timer cycle buffer register
Timer dead time data register
Timer general register A
Timer general register B
Timer general register E
Timer general register F
Timer general register V
Timer general register C
Timer general register D
Timer general register U
Interrupt request signals
Interrupt request signals
A/D conversion start signals
Channels 0 to 4: TRGAN
Channel 0:
Channel 4:
Internal data bus
Channel 3: TGIA_3
Channel 4: TGIA_4
Channel 5: TGIU_5
Channel 0: TGIA_0
Channel 1: TGIA_1
Channel 2: TGIA_2
TGIW_5
TGIB_3
TGIC_3
TGID_3
TGIB_4
TGIC_4
TGID_4
TGIV_5
TGIC_0
TGID_0
TCIV_3
TCIV_4
TGIB_0
TGIE_0
TGIF_0
TCIV_0
TGIB_1
TCIV_1
TCIU_1
TGIB_2
TCIV_2
TCIU_2
TRG4BN
TRG0N
TRG4AN