DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 637

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

(2) Programming Procedure in User Program Mode
The procedures for download, initialization, and programming are shown in figure 17.11.
The details of the programming procedure are described below. The procedure program must
be executed in an area other than the flash memory to be programmed. Especially the part
where the SCO bit in FCCS is set to 1 for downloading must be executed in the on-chip RAM.
Specify 1/4 (initial value) as the frequency division ratios of an internal clock (Iφ), a bus clock
(Bφ), and a peripheral clock (Pφ) through the frequency control register (FRQCR).
After the programming/erasing program has been downloaded and the SCO bit is cleared to 0,
the setting of the frequency control register (FRQCR) can be changed to the desired value. The
following description assumes the area to be programmed on the user MAT is erased and
program data is prepared in the consecutive area. When erasing has not been executed, carry
out erasing before writing.
JSR FTDAR setting + 32
set download destination
Select on-chip program
to be downloaded and
Set the FPEFEQ and
After clearing VBR,
FUBRA parameters
procedure program
execute download
set SCO to 1 and
Start programming
Set FKEY to H'A5
Clear FKEY to 0
DPFR = 0?
FPFR = 0?
Initialization
by FTDAR
1
Yes
Yes
Initialization error processing
Download error processing
Figure 17.11 Programming Procedure
No
No
(2.1)
(2.2)
(2.3)
(2.4)
(2.5)
(2.6)
(2.7)
(2.8)
No
Rev. 5.00 Mar. 06, 2009 Page 617 of 770
JSR FTDAR setting + 16
R5 (FMPAR and FMPDR)
Set parameter to R4 and
procedure program
End programming
Set FKEY to H'5A
Clear FKEY to 0
programming is
Programming
Required data
FPFR = 0?
completed?
1
Yes
Yes
Clear FKEY and
error processing
No
programming
REJ09B0243-0500
(2.9)
(2.10)
(2.11)
(2.12)
(2.13)
(2.14)