DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 694

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

19.3.7
RAMCR is an 8-bit readable/writable register that enables/disables the access to the on-chip
RAM.
Rev. 5.00 Mar. 06, 2009 Page 674 of 770
REJ09B0243-0500
Bit
7 to 5
4
3 to 0
RAM Control Register (RAMCR)
Bit Name
⎯
RAME
⎯
Initial value:
Initial
Value
All 0
1
All 0
R/W:
Bit:
R
7
0
-
R/W
R
R/W
R
R
6
0
-
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
RAM Enable
This bit enables/disables the on-chip RAM.
0: On-chip RAM disabled
1: On-chip RAM enabled
When this bit is cleared to 0, the access to the on-chip
RAM is disabled. In this case, an undefined value is
returned when reading or fetching the data or
instruction from the on-chip RAM, and writing to the on-
chip RAM is ignored.
When RAME is cleared to 0 to disable the on-chip
RAM, an instruction to access the on-chip RAM should
not be set next to the instruction to write RAMCR. If
such an instruction is set, normal access is not
guaranteed.
When RAME is set to 1 to enable the on-chip RAM, an
instruction to read RAMCR should be set next to the
instruction to write to RAMCR. If an instruction to
access the on-chip RAM is set next to the instruction to
write to RAMCR, normal access is not guaranteed.
Reserved
These bits are always read as 0. The write value should
always be 0.
R
5
0
-
RAME
R/W
4
1
R
3
0
-
R
2
0
-
R
1
0
-
R
0
0
-