DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 18

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

16.2 Port B ................................................................................................................................. 561
16.3 Port E ................................................................................................................................. 568
16.4 Port F ................................................................................................................................. 575
16.5 Usage Notes ....................................................................................................................... 577
Section 17 Flash Memory (ROM).......................................................................579
17.1 Features.............................................................................................................................. 579
17.2 Overview............................................................................................................................ 581
17.3 Input/Output Pins............................................................................................................... 587
17.4 Register Descriptions ......................................................................................................... 587
17.5 On-Board Programming Mode .......................................................................................... 611
17.6 Protection ........................................................................................................................... 624
17.7 Usage Notes ....................................................................................................................... 627
Rev. 5.00 Mar. 06, 2009 Page xvi of xviii
REJ09B0243-0500
16.1.3 Port A Port Register L (PAPRL) .......................................................................... 559
16.2.1 Register Descriptions............................................................................................ 561
16.2.2 Port B Data Registers H and L (PBDRH and PBDRL) ........................................ 562
16.2.3 Port B Port Registers H and L (PBPRH and PBPRL) .......................................... 565
16.3.1 Register Descriptions............................................................................................ 570
16.3.2 Port E Data Register L (PEDRL).......................................................................... 570
16.3.3 Port E Port Register L (PEPRL) ........................................................................... 573
16.4.1 Register Descriptions............................................................................................ 575
16.4.2 Port F Data Register L (PFDRL) .......................................................................... 576
16.5.1 Handling of Unused Pins ...................................................................................... 577
17.2.1 Block Diagram...................................................................................................... 581
17.2.2 Operating Mode .................................................................................................... 582
17.2.3 Mode Comparison ................................................................................................ 583
17.2.4 Flash Memory Configuration................................................................................ 584
17.2.5 Block Division ...................................................................................................... 584
17.2.6 Programming/Erasing Interface ............................................................................ 585
17.4.1 Registers ............................................................................................................... 587
17.4.2 Programming/Erasing Interface Registers ............................................................ 590
17.4.3 Programming/Erasing Interface Parameters ......................................................... 596
17.5.1 Boot Mode ............................................................................................................ 611
17.5.2 User Program Mode
17.6.1 Hardware Protection ............................................................................................. 624
17.6.2 Software Protection............................................................................................... 625
17.6.3 Error Protection .................................................................................................... 625
17.7.1 Interrupts during Programming/Erasing ............................................................... 627
17.7.2 Other Notes........................................................................................................... 629
(Only in On-Chip 128-Kbyte and 64-Kbyte ROM Version) ................................ 615