DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 59

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

2.5.3
Table 2.12 Arithmetic Operation Instructions
Instruction
ADD
ADD
ADDC
ADDV
CMP/EQ
CMP/EQ
CMP/HS
CMP/GE
CMP/HI
CMP/GT
CMP/PZ
CMP/PL
CMP/STR Rm,Rn
DIV1
DIV0S
DIV0U
DMULS.L Rm,Rn
Arithmetic Operation Instructions
Rm,Rn
#imm,Rn
Rm,Rn
Rm,Rn
#imm,R0
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rn
Rn
Rm,Rn
Rm,Rn
Operation
Rn + Rm → Rn
Rn + imm → Rn
Rn + Rm + T → Rn,
Carry → T
Rn + Rm → Rn,
Overflow → T
If R0 = imm, 1 → T
If Rn = Rm, 1 → T
If Rn ≥ Rm with
unsigned data, 1 → T
If Rn ≥ Rm with signed
data, 1 → T
If Rn > Rm with
unsigned data, 1 → T
If Rn > Rm with signed
data, 1 → T
If Rn ≥ 0, 1 → T
If Rn > 0, 1 → T
If Rn and Rm have an
equivalent byte, 1 → T
Single-step division
(Rn/Rm)
MSB of Rn → Q, MSB
of Rm → M, M^ Q → T
0 → M/Q/T
Signed operation of
Rn × Rm → MACH,
MACL 32 × 32 → 64 bits
Code
0011nnnnmmmm1100
0111nnnniiiiiiii
0011nnnnmmmm1110
0011nnnnmmmm1111
10001000iiiiiiii
0011nnnnmmmm0000
0011nnnnmmmm0010
0011nnnnmmmm0011
0011nnnnmmmm0110
0011nnnnmmmm0111
0100nnnn00010001
0100nnnn00010101
0010nnnnmmmm1100
0011nnnnmmmm0100
0010nnnnmmmm0111
0000000000011001
0011nnnnmmmm1101
Rev. 5.00 Mar. 06, 2009 Page 39 of 770
Execution
Cycles
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2 to 5*
REJ09B0243-0500
T Bit
⎯
⎯
Carry
Overflow
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Comparison
result
Calculation
result
Calculation
result
0
⎯