DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 443

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Bit
2
1, 0
Bit Name
TEIE
CKE[1:0]
Initial
value
0
00
R/W
R/W
R/W
Description
Transmit End Interrupt Enable
Enables or disables a transmit end interrupt (TEI) to be
issued when no valid transmit data is found in SCTDR
during MSB data transmission.
TEI can be canceled by clearing the TEND flag to 0 (by
clearing the TDRE flag in SCSSR to 0 after reading
TDRE = 1) or by clearing the TEIE bit to 0.
0: Transmit end interrupt request (TEI) is disabled
1: Transmit end interrupt request (TEI) is enabled
Clock Enable 1 and 0
Select the SCI clock source and enable or disable clock
output from the SCK pin. Depending on the
combination of CKE1 and CKE0, the SCK pin can be
used for serial clock output or serial clock input.
When selecting the clock output in clock synchronous
mode, set the C/A bit in SCSMR to 1 and then set bits
CKE1 and CKE0. For details on clock source selection,
see table 12.14 in section 12.4, Operation.
•
00: Internal clock, SCK pin used for input pin (The input
01: Internal clock, SCK pin used for clock output*
10: External clock, SCK pin used for clock input*
11: External clock, SCK pin used for clock input*
00: Internal clock, SCK pin used for synchronous clock
01: Internal clock, SCK pin used for synchronous clock
10: External clock, SCK pin used for synchronous clock
11: External clock, SCK pin used for synchronous clock
Notes: 1. The output clock frequency is 16 times the
Asynchronous mode
signal is ignored.)
output
output
input
input
Clock synchronous mode
2. The input clock frequency is 16 times the bit
bit rate.
rate.
Rev. 5.00 Mar. 06, 2009 Page 423 of 770
REJ09B0243-0500
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