DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 407

MCU RISC FLASH 32K 8K 64LQFP

DF71251AD50FPV

Manufacturer Part Number
DF71251AD50FPV
Description
MCU RISC FLASH 32K 8K 64LQFP
Manufacturer
Renesas Electronics America
Series
SuperH® SH Tinyr
Datasheet

Specifications of DF71251AD50FPV

Core Processor
SH-2
Core Size
32-Bit
Speed
50MHz
Connectivity
SCI
Peripherals
POR, PWM, WDT
Number Of I /o
37
Program Memory Size
32KB (32K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
DF71251AD50FPV
Manufacturer:
Renesas Electronics America
Quantity:
10 000
10.3.1
ICSR1 is a 16-bit readable/writable register that selects the POE0, POE1, and POE3 pin input
modes, controls the enable/disable of interrupts, and indicates status.
Initial value:
Bit
15
14
Notes:
R/W:
Bit:
1.
2.
POE3F
R/(W)*
Bit Name
POE3F
Writing 0 to this bit after reading it as 1 clears the flag and is the only allowed way.
Can be modified only once after a power-on reset.
Input Level Control/Status Register 1 (ICSR1)
15
0
1
R/(W)*
14
0
-
1
R/(W)*
POE1F POE0F
13
0
Initial
value
0
0
1
R/(W)*
12
0
1
R/W
R/(W)*
R/(W)*
11
R
0
-
10
R
0
-
1
1
Description
POE3 Flag
(Supported only by the SH7125.)
This flag indicates that a high impedance request has
been input to the POE3 pin.
[Setting condition]
Reserved
This bit is always read as 0. The write value should
always be 0.
[Clearing conditions]
R
9
0
-
By writing 0 to POE3F after reading POE3F = 1
(when the falling edge is selected by bits 7 and 6 in
ICSR1)
By writing 0 to POE3F after reading POE3F = 1 after
a high level input to POE3 is sampled at Pφ/8, Pφ/16,
or Pφ/128 clock (when low-level sampling is selected
by bits 7 and 6 in ICSR1)
When the input set by ICSR1 bits 7 and 6 occurs at
the POE3 pin
R/W R/W*
PIE1
8
0
POE3M[1:0]
7
0
2
R/W*
Rev. 5.00 Mar. 06, 2009 Page 387 of 770
6
0
2
R/W*
5
0
-
2
R/W*
4
0
-
2
R/W*
POE1M[1:0]
3
0
2
REJ09B0243-0500
R/W*
2
0
2
R/W*
POE0M[1:0]
1
0
2
R/W*
0
0
2

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