DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 225

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.3.8
TICCR is an 8-bit readable/writable register that specifies input capture conditions when TCNT_1
and TCNT_2 are cascaded. The MTU2 has one TICCR in channel 1.
Bit
0
Bit
7 to 4
3
Bit Name
TTSA
Bit Name
—
I2BE
Timer Input Capture Control Register (TICCR)
Initial value:
Initial
Value
0
Initial
Value
All 0
0
R/W:
Bit:
R
7
0
-
R/W
R/W
R/W
R
R/W
R
6
0
-
Description
Specifies the timing for transferring data from TGRC to
TGRA in each channel when they are used together for
buffer operation. When using channel 0 in other than
PWM mode, do not set this bit to 1.
0: When compare match A occurs in each channel
1: When TCNT is cleared in each channel
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Specifies whether to include the TIOC2B pin in the
TGRB_1 input capture conditions.
0: Does not include the TIOC2B pin in the TGRB_1
1: Includes the TIOC2B pin in the TGRB_1 input
Timing Select A
Input Capture Enable
R
5
0
-
capture conditions
input capture conditions
R
4
0
-
R/W
I2BE
3
0
R/W
I2AE
Rev. 5.00 Mar. 06, 2009 Page 205 of 770
2
0
R/W
I1BE
1
0
R/W
I1AE
0
0
REJ09B0243-0500