DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 13

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.4
9.5
9.6
9.3.11 Timer A/D Converter Start Request Cycle Set Buffer Registers
9.3.12 Timer Counter (TCNT)......................................................................................... 211
9.3.13 Timer General Register (TGR) ............................................................................. 211
9.3.14 Timer Start Register (TSTR) ................................................................................ 212
9.3.15 Timer Synchronous Register (TSYR)................................................................... 214
9.3.16 Timer Read/Write Enable Register (TRWER) ..................................................... 216
9.3.17 Timer Output Master Enable Register (TOER) .................................................... 217
9.3.18 Timer Output Control Register 1 (TOCR1) .......................................................... 218
9.3.19 Timer Output Control Register 2 (TOCR2) .......................................................... 221
9.3.20 Timer Output Level Buffer Register (TOLBR) .................................................... 224
9.3.21 Timer Gate Control Register (TGCR) .................................................................. 225
9.3.22 Timer Subcounter (TCNTS) ................................................................................. 227
9.3.23 Timer Dead Time Data Register (TDDR)............................................................. 228
9.3.24 Timer Cycle Data Register (TCDR) ..................................................................... 228
9.3.25 Timer Cycle Buffer Register (TCBR)................................................................... 229
9.3.26 Timer Interrupt Skipping Set Register (TITCR) ................................................... 229
9.3.27 Timer Interrupt Skipping Counter (TITCNT)....................................................... 231
9.3.28 Timer Buffer Transfer Set Register (TBTER) ...................................................... 232
9.3.29 Timer Dead Time Enable Register (TDER).......................................................... 234
9.3.30 Timer Waveform Control Register (TWCR) ........................................................ 235
9.3.31 Bus Master Interface............................................................................................. 236
Operation ........................................................................................................................... 237
9.4.1
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
9.4.7
9.4.8
9.4.9
9.4.10 External Pulse Width Measurement...................................................................... 314
9.4.11 Dead Time Compensation .................................................................................... 315
9.4.12 TCNT Capture at Crest and/or Trough in Complementary PWM Operation ....... 317
Interrupt Sources................................................................................................................ 318
9.5.1
9.5.2
Operation Timing............................................................................................................... 323
9.6.1
(TADCOBRA_4 and TADCOBRB_4) ................................................................ 210
Basic Functions..................................................................................................... 237
Synchronous Operation......................................................................................... 243
Buffer Operation................................................................................................... 245
Cascaded Operation .............................................................................................. 249
PWM Modes......................................................................................................... 254
Phase Counting Mode........................................................................................... 259
Reset-Synchronized PWM Mode ......................................................................... 266
Complementary PWM Mode................................................................................ 269
A/D Converter Start Request Delaying Function.................................................. 310
Interrupt Sources and Priorities ............................................................................ 318
A/D Converter Activation..................................................................................... 321
Input/Output Timing ............................................................................................. 323
Rev. 5.00 Mar. 06, 2009 Page xi of xviii
REJ09B0243-0500