DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 17

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 Compare Match Timer (CMT) ..........................................................505
14.1 Features.............................................................................................................................. 505
14.2 Register Descriptions ......................................................................................................... 506
14.3 Operation ........................................................................................................................... 510
14.4 Interrupts............................................................................................................................ 511
14.5 Usage Notes ....................................................................................................................... 512
Section 15 Pin Function Controller (PFC)...........................................................515
15.1 Register Descriptions ......................................................................................................... 523
15.2 Usage Notes ....................................................................................................................... 552
Section 16 I/O Ports.............................................................................................553
16.1 Port A................................................................................................................................. 554
13.7.4 Range of Analog Power Supply and Other Pin Settings....................................... 502
13.7.5 Notes on Board Design ......................................................................................... 502
13.7.6 Notes on Noise Countermeasures ......................................................................... 503
14.2.1 Compare Match Timer Start Register (CMSTR) .................................................. 507
14.2.2 Compare Match Timer Control/Status Register (CMCSR) .................................. 507
14.2.3 Compare Match Counter (CMCNT) ..................................................................... 509
14.2.4 Compare Match Constant Register (CMCOR) ..................................................... 509
14.3.1 Interval Count Operation ...................................................................................... 510
14.3.2 CMCNT Count Timing......................................................................................... 510
14.4.1 CMT Interrupt Sources ......................................................................................... 511
14.4.2 Timing of Setting Compare Match Flag ............................................................... 511
14.4.3 Timing of Clearing Compare Match Flag............................................................. 511
14.5.1 Module Standby Mode Setting ............................................................................. 512
14.5.2 Conflict between Write and Compare-Match Processes of CMCNT ................... 512
14.5.3 Conflict between Word-Write and Count-Up Processes of CMCNT ................... 513
14.5.4 Conflict between Byte-Write and Count-Up Processes of CMCNT..................... 514
14.5.5 Compare Match between CMCNT and CMCOR ................................................. 514
15.1.1 Port A I/O Register L (PAIORL).......................................................................... 524
15.1.2 Port A Control Registers L1 to L4 (PACRL1 to PACRL4).................................. 524
15.1.3 Port B I/O Registers L and H (PBIORL and PBIORH)........................................ 535
15.1.4 Port B Control Registers L1, L2, and H1 (PBCRL1, PBCRL2, and PBCRH1) ... 536
15.1.5 Port E I/O Register L (PEIORL)........................................................................... 541
15.1.6 Port E Control Registers L1 to L4 (PECRL1 to PECRL4) ................................... 541
15.1.7 IRQOUT Function Control Register (IFCR) ........................................................ 551
16.1.1 Register Descriptions............................................................................................ 555
16.1.2 Port A Data Register L (PADRL) ......................................................................... 555
Rev. 5.00 Mar. 06, 2009 Page xv of xviii
REJ09B0243-0500