DF71251AD50FPV Renesas Electronics America, DF71251AD50FPV Datasheet - Page 269

• Manufacturer Part Number: DF71251AD50FPV
• Description: MCU RISC FLASH 32K 8K 64LQFP
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH Tinyr

Specifications of DF71251AD50FPV

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 50MHz
• Connectivity: SCI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

9.4.4
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 counter clock upon overflow/underflow of
TCNT_2 as set in bits TPSC0 to TPSC2 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 9.44 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1, the counter clock setting is invalid and the
Table 9.44 Cascaded Combinations
For simultaneous input capture of TCNT_1 and TCNT_2 during cascaded operation, additional
input capture input pins can be specified by the input capture control register (TICCR). For input
capture in cascade connection, refer to section 9.7.22, Simultaneous Capture of TCNT_1 and
TCNT_2 in Cascade Connection.
Figure 9.19 Example of Buffer Operation When TCNT_0 Clearing is Selected for TGRC_0
Combination
Channels 1 and 2
TGRC_0
TGRB_0
TGRA_0
TGRA_0
counters operates independently in phase counting mode.
H'0000
TIOCA
TCNT_0 value
Cascaded Operation
H'0200
H'0200
H'0200
Upper 16 Bits
TCNT_1
to TGRA_0 Transfer Timing
H'0450
H'0450
Transfer
H'0450
Lower 16 Bits
TCNT_2
Rev. 5.00 Mar. 06, 2009 Page 249 of 770
H'0520
H'0520
REJ09B0243-0500
H'0520
Time